基于FPGA的数码管动态扫描程序与按键消抖程序

数码管动态扫描程序

/*
Author   : yffdd
time     : 2022/01/30
function : 数码管动态扫描
测试芯片  : AX301---6位共阳8段数码管
显示字符  :
          seg_date = 5'd0 : 字符'0'
          seg_date = 5'd1 : 字符'1'
          seg_date = 5'd2 : 字符'2'
          seg_date = 5'd3 : 字符'3'
          seg_date = 5'd4 : 字符'4'
          seg_date = 5'd5 : 字符'5'
          seg_date = 5'd6 : 字符'6'
          seg_date = 5'd7 : 字符'7'
          seg_date = 5'd8 : 字符'8'
          seg_date = 5'd9 : 字符'9'
          seg_date = 5'd10: 字符'A'
          seg_date = 5'd11: 字符'B'
          seg_date = 5'd12: 字符'C'
          seg_date = 5'd13: 字符'D'
          seg_date = 5'd14: 字符'E'
          seg_date = 5'd15: 字符'F'
          seg_date = 5'd16: 字符'-' 短横线
          seg_date = 5'd17: 字符'_' 下划线
          seg_date = 5'd31: 不显示任何字符
          PS：可自行更改段选表显示其它需要的字符
模块例化：
    seg_scan seg_scan_inst (
        .clk            (clk            ),
        .rst_n          (rst_n          ),
        .seg_sel        (seg_sel        ),
        .seg_bin        (seg_bin        ),
        .seg_date_0     (seg_date_0     ),
        .seg_date_1     (seg_date_1     ),
        .seg_date_2     (seg_date_2     ),
        .seg_date_3     (seg_date_3     ),
        .seg_date_4     (seg_date_4     ),
        .seg_date_5     (seg_date_5     )
    );
*/

module seg_scan(
    input                    clk            ,
    input                    rst_n          ,
    output  reg    [ 5:0]    seg_sel        ,//数码管位选号
    output  reg    [ 7:0]    seg_bin        ,//数码管段选值
    input          [ 4:0]    seg_date_0     ,//0号数码管显示值
    input          [ 4:0]    seg_date_1     ,//1号数码管显示值
    input          [ 4:0]    seg_date_2     ,//2号数码管显示值
    input          [ 4:0]    seg_date_3     ,//3号数码管显示值
    input          [ 4:0]    seg_date_4     ,//4号数码管显示值
    input          [ 4:0]    seg_date_5      //5号数码管显示值
    );

    reg            [ 7:0]    seg_bin_0      ;//0号数码管段选值
    reg            [ 7:0]    seg_bin_1      ;//1号数码管段选值
    reg            [ 7:0]    seg_bin_2      ;//2号数码管段选值
    reg            [ 7:0]    seg_bin_3      ;//2号数码管段选值
    reg            [ 7:0]    seg_bin_4      ;//4号数码管段选值
    reg            [ 7:0]    seg_bin_5      ;//5号数码管段选值

    
    parameter      SCAN_CLK   = 1000                  ;//扫描频率，每秒扫描1000次
    parameter      SYS_CLK    = 50000000              ;//系统时钟频率
    parameter      SCAN_COUNT = SYS_CLK / SCAN_CLK - 1;

    reg            [31:0]    scan_time      ;//扫描时间
    reg            [ 3:0]    scan_sel       ;//数码管位选控制信号
    
    //动态扫描
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)begin
            scan_time <= 32'd0;
            scan_sel  <= 4'd0;
        end
        else if(scan_time >= SCAN_COUNT)begin
            scan_time <= 32'd0;
            if(scan_sel == 4'd5)
                scan_sel  <= 4'd0;
            else
                scan_sel  <= scan_sel + 4'd1;
        end
        else begin
                scan_time <= scan_time + 32'd1;
        end
    end

    //位选段选值控制
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)begin
            seg_sel <= 6'b111111;
            seg_bin <= 8'hff;
        end
        else begin
            case(scan_sel)//第0个数码管
                4'd0:begin
                    seg_sel <= 6'b11_1110;
                    seg_bin <= seg_bin_0;
                end
                4'd1:begin//第1个数码管
                    seg_sel <= 6'b11_1101;
                    seg_bin <= seg_bin_1;
                end
                4'd2:begin//第2个数码管
                    seg_sel <= 6'b11_1011;
                    seg_bin <= seg_bin_2;
                end
                4'd3:begin//第3个数码管
                    seg_sel <= 6'b11_0111;
                    seg_bin <= seg_bin_3;
                end
                4'd4:begin//第4个数码管
                    seg_sel <= 6'b10_1111;
                    seg_bin <= seg_bin_4;
                end
                4'd5:begin//第5个数码管
                    seg_sel <= 6'b01_1111;
                    seg_bin <= seg_bin_5;
                end
                default:begin
                    seg_sel <= 6'b11_1111;
                    seg_bin <= 8'hff;
                end
            endcase
        end
    end

    //数码管第0位的段选设置
    always@(*)begin
        case(seg_date_0)
            5'd0   :seg_bin_0 <= 8'b1100_0000;
            5'd1   :seg_bin_0 <= 8'b1111_1001;
            5'd2   :seg_bin_0 <= 8'b1010_0100;
            5'd3   :seg_bin_0 <= 8'b1011_0000;
            5'd4   :seg_bin_0 <= 8'b1001_1001;
            5'd5   :seg_bin_0 <= 8'b1001_0010;
            5'd6   :seg_bin_0 <= 8'b1000_0010;
            5'd7   :seg_bin_0 <= 8'b1111_1000;
            5'd8   :seg_bin_0 <= 8'b1000_0000;
            5'd9   :seg_bin_0 <= 8'b1001_0000;
            5'd10  :seg_bin_0 <= 8'b1000_1000;
            5'd11  :seg_bin_0 <= 8'b1000_0011;
            5'd12  :seg_bin_0 <= 8'b1100_0110;
            5'd13  :seg_bin_0 <= 8'b1010_0001;
            5'd14  :seg_bin_0 <= 8'b1000_0110;
            5'd15  :seg_bin_0 <= 8'b1000_1110;
            5'd16  :seg_bin_0 <= 8'b1011_1111;
            5'd17  :seg_bin_0 <= 8'b1111_0111;
            5'd31  :seg_bin_0 <= 8'b1111_1111;
            default:seg_bin_0 <= 8'b1111_1111;
        endcase
    end

    //数码管第1位的段选设置
    always@(*)begin
        case(seg_date_1)
            5'd0   :seg_bin_1 <= 8'b1100_0000;
            5'd1   :seg_bin_1 <= 8'b1111_1001;
            5'd2   :seg_bin_1 <= 8'b1010_0100;
            5'd3   :seg_bin_1 <= 8'b1011_0000;
            5'd4   :seg_bin_1 <= 8'b1001_1001;
            5'd5   :seg_bin_1 <= 8'b1001_0010;
            5'd6   :seg_bin_1 <= 8'b1000_0010;
            5'd7   :seg_bin_1 <= 8'b1111_1000;
            5'd8   :seg_bin_1 <= 8'b1000_0000;
            5'd9   :seg_bin_1 <= 8'b1001_0000;
            5'd10  :seg_bin_1 <= 8'b1000_1000;
            5'd11  :seg_bin_1 <= 8'b1000_0011;
            5'd12  :seg_bin_1 <= 8'b1100_0110;
            5'd13  :seg_bin_1 <= 8'b1010_0001;
            5'd14  :seg_bin_1 <= 8'b1000_0110;
            5'd15  :seg_bin_1 <= 8'b1000_1110;
            5'd16  :seg_bin_1 <= 8'b1011_1111;
            5'd17  :seg_bin_1 <= 8'b1111_0111;
            5'd31  :seg_bin_0 <= 8'b1111_1111;
            default:seg_bin_1 <= 8'b1111_1111;
        endcase
    end

    //数码管第2位的段选设置
    always@(*)begin
        case(seg_date_2)
            5'd0   :seg_bin_2 <= 8'b1100_0000;
            5'd1   :seg_bin_2 <= 8'b1111_1001;
            5'd2   :seg_bin_2 <= 8'b1010_0100;
            5'd3   :seg_bin_2 <= 8'b1011_0000;
            5'd4   :seg_bin_2 <= 8'b1001_1001;
            5'd5   :seg_bin_2 <= 8'b1001_0010;
            5'd6   :seg_bin_2 <= 8'b1000_0010;
            5'd7   :seg_bin_2 <= 8'b1111_1000;
            5'd8   :seg_bin_2 <= 8'b1000_0000;
            5'd9   :seg_bin_2 <= 8'b1001_0000;
            5'd10  :seg_bin_2 <= 8'b1000_1000;
            5'd11  :seg_bin_2 <= 8'b1000_0011;
            5'd12  :seg_bin_2 <= 8'b1100_0110;
            5'd13  :seg_bin_2 <= 8'b1010_0001;
            5'd14  :seg_bin_2 <= 8'b1000_0110;
            5'd15  :seg_bin_2 <= 8'b1000_1110;
            5'd16  :seg_bin_2 <= 8'b1011_1111;
            5'd17  :seg_bin_2 <= 8'b1111_0111;
            5'd31  :seg_bin_0 <= 8'b1111_1111;
            default:seg_bin_2 <= 8'b1111_1111;
        endcase
    end

    //数码管3位的段选设置
    always@(*)begin
        case(seg_date_3)
            5'd0   :seg_bin_3 <= 8'b1100_0000;
            5'd1   :seg_bin_3 <= 8'b1111_1001;
            5'd2   :seg_bin_3 <= 8'b1010_0100;
            5'd3   :seg_bin_3 <= 8'b1011_0000;
            5'd4   :seg_bin_3 <= 8'b1001_1001;
            5'd5   :seg_bin_3 <= 8'b1001_0010;
            5'd6   :seg_bin_3 <= 8'b1000_0010;
            5'd7   :seg_bin_3 <= 8'b1111_1000;
            5'd8   :seg_bin_3 <= 8'b1000_0000;
            5'd9   :seg_bin_3 <= 8'b1001_0000;
            5'd10  :seg_bin_3 <= 8'b1000_1000;
            5'd11  :seg_bin_3 <= 8'b1000_0011;
            5'd12  :seg_bin_3 <= 8'b1100_0110;
            5'd13  :seg_bin_3 <= 8'b1010_0001;
            5'd14  :seg_bin_3 <= 8'b1000_0110;
            5'd15  :seg_bin_3 <= 8'b1000_1110;
            5'd16  :seg_bin_3 <= 8'b1011_1111;
            5'd17  :seg_bin_3 <= 8'b1111_0111;
            5'd31  :seg_bin_0 <= 8'b1111_1111;
            default:seg_bin_3 <= 8'b1111_1111;
        endcase
    end

    //数码管第4位的段选设置
    always@(*)begin
        case(seg_date_4)
            5'd0   :seg_bin_4 <= 8'b1100_0000;
            5'd1   :seg_bin_4 <= 8'b1111_1001;
            5'd2   :seg_bin_4 <= 8'b1010_0100;
            5'd3   :seg_bin_4 <= 8'b1011_0000;
            5'd4   :seg_bin_4 <= 8'b1001_1001;
            5'd5   :seg_bin_4 <= 8'b1001_0010;
            5'd6   :seg_bin_4 <= 8'b1000_0010;
            5'd7   :seg_bin_4 <= 8'b1111_1000;
            5'd8   :seg_bin_4 <= 8'b1000_0000;
            5'd9   :seg_bin_4 <= 8'b1001_0000;
            5'd10  :seg_bin_4 <= 8'b1000_1000;
            5'd11  :seg_bin_4 <= 8'b1000_0011;
            5'd12  :seg_bin_4 <= 8'b1100_0110;
            5'd13  :seg_bin_4 <= 8'b1010_0001;
            5'd14  :seg_bin_4 <= 8'b1000_0110;
            5'd15  :seg_bin_4 <= 8'b1000_1110;
            5'd16  :seg_bin_4 <= 8'b1011_1111;
            5'd17  :seg_bin_4 <= 8'b1111_0111;
            5'd31  :seg_bin_0 <= 8'b1111_1111;
            default:seg_bin_4 <= 8'b1111_1111;
        endcase
    end

    //数码管第5位的段选设置
    always@(*)begin
        case(seg_date_5)
            5'd0   :seg_bin_5 <= 8'b1100_0000;
            5'd1   :seg_bin_5 <= 8'b1111_1001;
            5'd2   :seg_bin_5 <= 8'b1010_0100;
            5'd3   :seg_bin_5 <= 8'b1011_0000;
            5'd4   :seg_bin_5 <= 8'b1001_1001;
            5'd5   :seg_bin_5 <= 8'b1001_0010;
            5'd6   :seg_bin_5 <= 8'b1000_0010;
            5'd7   :seg_bin_5 <= 8'b1111_1000;
            5'd8   :seg_bin_5 <= 8'b1000_0000;
            5'd9   :seg_bin_5 <= 8'b1001_0000;
            5'd10  :seg_bin_5 <= 8'b1000_1000;
            5'd11  :seg_bin_5 <= 8'b1000_0011;
            5'd12  :seg_bin_5 <= 8'b1100_0110;
            5'd13  :seg_bin_5 <= 8'b1010_0001;
            5'd14  :seg_bin_5 <= 8'b1000_0110;
            5'd15  :seg_bin_5 <= 8'b1000_1110;
            5'd16  :seg_bin_5 <= 8'b1011_1111;
            5'd17  :seg_bin_5 <= 8'b1111_0111;
            5'd31  :seg_bin_0 <= 8'b1111_1111;
            default:seg_bin_5 <= 8'b1111_1111;
        endcase
    end

endmodule

按键消抖程序

/*
Author   : yffdd
time     : 2022/01/30
function : 按键消抖检测模块
使用方法：   模块例化之后，检测key_fs标志即可检测消抖后的按键输入，key_fs高电平有效

模块例化：
    key_filter key_filter_inst(
        .clk            (clk            ),
        .rst_n          (rst_n          ),
        .key_in         (key_in         ),
        .key_fs         (key_fs         )
    );
*/

module key_filter(
    input                    clk            ,
    input                    rst_n          ,
    input                    key_in         ,//按键输入
    output  reg              key_fs          //按键返回值，按下1次有一个时钟周期的高电平脉冲
);

    reg                      key_flag       ;//按键按下标志
    reg                      key_state      ;//滤波后按键理想状态
    
    reg            [ 3:0]    state          ;//按键状态变量
    reg            [19:0]    cnt_20ms       ;//20ms计数
    reg                      en_cnt         ;//20ms定时使能计数寄存器
    reg            key_tmpa, key_tmpb       ;//按键在两个相邻时钟上升沿的状态
    wire           pedge,    nedge          ;//按键上升沿与下降沿
    reg                      cnt_full       ;//计数满标志信号
    reg            key_in_sa,key_in_sb      ;//按键在两个相邻时钟上升沿的状态

    localparam
        IDEL    = 4'b0001,//空闲状态
        FILTER0 = 4'b0010,//按下抖动状态
        DOWN    = 4'b0100,//按下稳定状态
        FILTER1 = 4'b1000;//释放抖动状态    
    
    
    //对外部输入的异步信号进行同步处理
    always@(posedge clk or negedge rst_n)
        if(rst_n == 1'b0)begin
            key_in_sa <= 1'b0;
            key_in_sb <= 1'b0;
        end
        else begin
            key_in_sa <= key_in;
            key_in_sb <= key_in_sa;
        end
    
    //使用D触发器存储两个相邻时钟上升沿时外部输入信号（已经同步到系统时钟域中）的电平状态
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)begin
            key_tmpa <= 1'b0;
            key_tmpb <= 1'b0;
        end
        else begin
            key_tmpa <= key_in_sb;
            key_tmpb <= key_tmpa;    
        end
    end

    //产生跳变沿信号
    assign nedge = key_tmpa & (!key_tmpb);//按键下降沿
    assign pedge = !key_tmpa & key_tmpb  ;//按键上升沿
    
    //按键状态判断
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)begin
            en_cnt    <= 1'b0;
            state     <= IDEL;
            key_flag  <= 1'b0;
            key_state <= 1'b1;
        end
        else begin
            case(state)
                IDEL   :begin
                        key_flag   <= 1'b0;
                        if(nedge)begin
                            state  <= FILTER0;
                            en_cnt <= 1'b1;
                        end
                        else
                            state  <= IDEL;
                end
                        
                FILTER0:begin
                        if(cnt_full)begin
                            key_flag  <= 1'b1;
                            key_state <= 1'b0;
                            en_cnt    <= 1'b0;
                            state     <= DOWN;
                        end
                        else if(pedge)begin
                            state     <= IDEL;
                            en_cnt    <= 1'b0;
                        end
                        else
                            state     <= FILTER0;
                end
                        
                DOWN  :begin
                        key_flag   <= 1'b0;
                        if(pedge)begin
                            state  <= FILTER1;
                            en_cnt <= 1'b1;
                        end
                        else
                            state  <= DOWN;
                end
                
                FILTER1:begin
                        if(cnt_full)begin
                            key_flag  <= 1'b1;
                            key_state <= 1'b1;
                            en_cnt    <= 1'b0;
                            state     <= IDEL;
                        end
                        else if(nedge)begin
                            en_cnt    <= 1'b0;
                            state     <= DOWN;
                        end
                        else
                            state     <= FILTER1;
                end

                default:begin 
                        state     <= IDEL; 
                        en_cnt    <= 1'b0;        
                        key_flag  <= 1'b0;
                        key_state <= 1'b1;
                end
            endcase    
        end
    end
    
    //按键标志处理
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)begin
            key_fs <= 0;
        end
        else begin
            key_fs <= key_flag && (!key_state);
        end
    end
    
    //20ms计数
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)
            cnt_20ms <= 20'd0;
        else if(en_cnt)
            cnt_20ms <= cnt_20ms + 1'b1;
        else
            cnt_20ms <= 20'd0;
    end

    //20ms计数满
    always@(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)
            cnt_full <= 1'b0;
        else if(cnt_20ms == 999_999)
            cnt_full <= 1'b1;
        else
            cnt_full <= 1'b0;
    end
endmodule