试验四 数码管控制实验

1，循环显示1-F。

module Seven_LED( 
              clk,
              rst,
              led_out
                );
           
input  clk,rst;
output [11:0] led_out;
reg    [11:0] led_out;
   
reg  [3:0] data;
reg [24:0] Mega_cnt;
wire       slow_clk;

/***********************************/
always @(posedge clk or negedge rst)
begin
if(!rst)
  begin
  Mega_cnt<=0;
  end
else
  begin
  Mega_cnt<=Mega_cnt+1;
  end
end

assign slow_clk = Mega_cnt[24];
/***********************************/

always @ (posedge slow_clk or negedge rst)
   begin
     if(!rst)
        data <= 0;
     else 
        data <= data + 1;
   end


always @ (data)
   case(data)
   4'd0 : led_out = 12'b1111_1100_1111;
   4'd1 : led_out = 12'b0110_0000_1111;
   4'd2 : led_out = 12'b1101_1010_1111;
   4'd3 : led_out = 12'b1111_0010_1111;
   4'd4 : led_out = 12'b0110_0110_1111;
   4'd5 : led_out = 12'b1011_0110_1111;
   4'd6 : led_out = 12'b1011_1110_1111;
   4'd7 : led_out = 12'b1110_0000_1111;
   4'd8 : led_out = 12'b1111_1110_1111;
   4'd9 : led_out = 12'b1111_0110_1111;
   4'd10: led_out = 12'b1110_1110_1111;
   4'd11: led_out = 12'b0011_1110_1111;
   4'd12: led_out = 12'b1001_1100_1111;
   4'd13: led_out = 12'b0111_1010_1111;
   4'd14: led_out = 12'b1001_1110_1111;
   4'd15: led_out = 12'b1000_1110_1111;
endcase

endmodule

2，显示1234

module seg_led(clk,rst,
			s0,s1,s2,s3,
			d0,d1,d2,d3,d4,d5,d6,d7
			);

	input      clk,rst       ;
	output     s0,s1,s2,s3   ;
	output     d0,d1,d2,d3,d4,d5,d6,d7 ;

	reg [1 :0 ] state ;
	reg [3 :0 ] sn ;
	reg [7 :0 ] data ;
	reg [15:0 ] cnt ;
	
	wire       s0,s1,s2,s3   ;
	wire       d0,d1,d2,d3,d4,d5,d6,d7 ; 

	assign     {s3,s2,s1,s0} = sn ;
	assign     {d7,d6,d5,d4,d3,d2,d1,d0} = data ;

	always @ ( posedge clk )
		if( !rst )
			cnt<=16'b0;
		else
			cnt<=cnt+16'b1;

	wire clk_slow = cnt[15] ;

	always @ ( posedge clk_slow or negedge rst )
		if( !rst )
			state<=2'b00;
		else
			state<=state+2'b01;

	always @ ( posedge clk_slow or negedge rst )
		if( !rst )
			begin
				sn<=4'b0;
				data<=8'b0;
			end
		else
			case(state)
				2'b00:
					begin
						sn<=4'b0001;
						data<=8'b0110_0000;
					end
				2'b01:
					begin
						sn<=4'b0010;
						data<=8'b1101_1010;
					end
				2'b10:
					begin
						sn<=4'b0100;
						data<=8'b1111_0010;
					end
				2'b11:
					begin
						sn<=4'b1000;
						data<=8'b0110_0110;
					end
			endcase


endmodule

 动态扫描的方法显示。