HDLBits——Verilog刷题之旅（二）

老师在上课，我在下面刷题，可真刺激

题目3

• 文字描述
  You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.
  The module provided to you is: module my_dff ( input clk, input d, output q );
  Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

• 图示
  

• 代码

	module top_module ( input clk, input d, output q );
    	wire a,b;
    	my_dff instance1 ( clk, d, a);
    	my_dff instance2 ( clk, a, b);
    	my_dff instance3 ( clk, b, q);
	endmodule

• 结果

  

• 心得
  verilog不能像C++那样，一次定义多个变量再进行赋值，e.g. my_dff a, b, c;

题目4

• 文字描述
  In this exercise, you will create a circuit with two levels of hierarchy. Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1.
  Like module_add, you are given a module add16 that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored).
  Connect the add16 modules together as shown in the diagram below. The provided module add16 has the following declaration:
  module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

  Within each add16, 16 full adders (module add1, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:
  module add1 ( input a, input b, input cin, output sum, output cout );

  Recall that a full adder computes the sum and carry-out of a+b+cin.
  In summary, there are three modules in this design:
  top_module — Your top-level module that contains two of…
  add16, provided — A 16-bit adder module that is composed of 16 of…
  add1 — A 1-bit full adder module.

  If your submission is missing a module add1, you will get an error message that says Error (12006): Node instance “user_fadd[0].a1” instantiates undefined entity “add1”.

• 图示
  

• 代码

	module top_module (
	input [31:0] a,
	input [31:0] b,
	output [31:0] sum
	);
		wire c;
        add16 instance1( a[15:0], b[15:0], 0, sum[15:0], c );
        add16 instance2( a[31:16], b[31:16], c, sum[31:16], );
 
	endmodule
 
    module add1 ( input a, input b, input cin, output sum, output cout);

        assign sum = a^b^cin;
        assign cout = (a & b) || (a & cin) || (b & cin);

    endmodule

• 结果

  

• 心得
  温习了一下上学期学的全加器，我可真捞orz