Synopsys DC约束语法检查和报告查看

1约束语法检测

dcprocheck TOP.con

2 Verify port constraints (non-clock)

report_port -verbose

3 Verify clock constraints

report_clock -- clock waveform
report_clock –skew -- clocktree specs

check_timing

1）时间预算缺少端点约束

2）丢失、重叠或多个时钟

3）可能干扰时钟的时钟选通信号