Lab 2 - Task v2 SP_22-设计complex multiplication共3个part-verilog设计

基本要求：
CMPEN/EE 417
Due
Clarifications
●This lab and all future labs will be completed in your groups unless otherwise specified.
○One person should submit from your group. All other member should submit just the full name of the individual who has submitted everything
●Part 2/3: Write complex multiplier code based on the DSP complex multiplier on the slides.
○However, the number of cycles it takes your module to get a result may be any (reasonable) number. It very likely should match or be close to what’s in the testbench file already.
○If your designs do not simulate with an unmodified version of the testbench file then you will lose points!
Purpose
The purpose of this lab is to provide experience creating pipelined designs as well as learning how to use built in FPGA features to create performance oriented designs.
Task
In this lab you will create a complex-number multiplier module. Follow the design gi