最近使用芯片的RAPIDIO IP，查找相关IP的问题。对IP进行了一定的了解后编写该读书笔记。后续相关人员能够更简单的学习和理解这个IP。

文档说明

IP文档分为2个部分，分别为GRIO_Datasheet和RapidIO to AXI Bridge Controller_Datasheet，两个文档分别说明整个IP的2个部分功能。从下面图可以明确的区分两个部分，ULI的左边Generic RapidIO Conterllr 简称GRIO右边为RapidIO to AXI Bridge Controller_Datasheet简称RAB。

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GRIO （Generic RapidIO Conterllr）简介

GRIO is partitioned into inbound and outbound blocks, and these blocks are further partitioned into three implementation layers:
1.Physical Layer
2.Logical Layer

对于软件来说该部分主要在初始化阶段会接触到，比如与PHY相关的初始化，链路状态，主从初始化等，后续数据传输基本不用再修改这个部分的设置和寄存器。细节在后续GRIO 程序分析的文章中我再认真分析初始化的相关过程。

从输出方向来看相关的内容，输入方向类似。
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RapidIO 互连规范。物理 PCS 和物理协议层主要解决 RapidIO 互连规范中标题为“LP-Serial Physical层”。在 GRIO 中，逻辑层实现了逻辑和传输层协议规范。

Physical Layer 物理层

物理层标准的一些知识可以该链接了解一下
SERDES分为PCS（物理编码子层）和PMA（物理媒介附属子层）两层，其中PCS是由纯数字电路组成，可以用软逻辑来实现，而PMA则既包括了数字电路，也包括了模拟电路，不能用纯逻辑实现。

Physical PCS功能

PCS功能
Physical PCS
1.BRC1 and BRC2
• Provides alignment of the received bit stream to 10b code-group boundaries
• 8b/10b Encoding and Decoding
2.BRC3
• Provides alignment of the received bit stream to 67b code-group boundaries
• 64B/67B Encoding and Decoding

Physical Protocol功能

该部分主要和底层的LVDS PHY 相连。
The Physical Layer protocol defines a full duplex LP-Serial and 8/16 bit LP-LVDS physical layer interface (link) between devices using unidirectional differential signals in each direction. It implements a protocol for link management and packet transport over a link.

Logical Protocol Layer逻辑层

基本属性
• Supports RIO Logical and Common Transport Layer functionality
• Supports both Input/Output Logical and Message Passing Logical protocols
• Supports up to 256 Bytes data payload
• Supports 64/128/256-bit internal data path
• Supports pipelined ULI
• Supports all transport sizes (DevID 8/DevID 16/DevID 32)
• Supports 34-bit and 50-bit (hardware configurable) addressing
• Supports hardware-configurable outstanding unacknowledged RIO transactions
• Supports all transaction flows and all priorities
• Supports encapsulation of RIO packet
基本功能：
The Logical Layer implements the logical and transport layer protocols. It controls the ordering of the received and transmitted packets and exchanges flow control information with the
Logical Layer of the device on the other side of the link.
1.Sends and receives packets between Physical Layer and ULI controller
2.Controls the ordering of the received and transmitted packets
3.Exchanges flow control information with the Logical Layer of the device on the other side of the link

RAB （RapidIO to AXI Bridge ）介绍

其实RAB 这个部分GRIO部分容易明白，他的功能主要实现的是下面一些传输功能，特别时一些传输映射窗口的设置容易让人比较混乱。对应RAB 后续的文章描述会说明，主要会分为初始化、 PIO设置（APIO和RIO映射关系的设置)，DMA操作、Message 生成和处理几个部分来说。

The AXI-RIO Bridge connects to RapidIO on one side and AMBA sub system on the other side. The following types of transfers are supported
1.AXI PIO (AXI Slave): Request is transferred from AXI to RapidIO. The bridge acts as AXI Write/Read Slave and RapidIO Initiator.
2.RIO PIO (AXI Master): Request is transferred from RapidIO to AXI. The bridge acts as RapidIO Target and AXI Write/Read Master. Additionally it handles optional Inbound and Outbound Messaging.
3.Write DMA (optional): Data is transferred from AXI to RapidIO. The bridge acts as AXI Read Master and RapidIO Write Initiator
4.Read DMA (optional): Data is transferred from RapidIO to AXI. The bridge acts as RapidIO Read Initiator and AXI Write Master.
5.Data Message (Optional): For Inbound Data messaging Bridge acts as RapidIO target and AXI Write Master. It also sends out responses towards RapidIO Fabric as RapidIO Initiator. For Outbound Data message it acts as AXI Read Master and RapidIO initiator.
6.Doorbell (Optional): For Inbound DB Bridge acts as RapidIO target and optionally either as AXI Write Master or APB CSR Slave or none (generates physical signal for Inbound DB). For Outbound Doorbell, it acts as APB CSR Slave and RapidIO initiator.
7.Data Stream (Optional): For Inbound Data Stream Bridge acts as RapidIO target and AXI Write Master. For Outbound Data Stream it acts as AXI Read Master and RapidIO initiator.In addition, RapidIO Configuration Space and device specific Control/Status/Debug register can be accessed by either RapidIO Host through RapidIO link, or AXI Master through AXI Write/Read
Slave Interface (or APB interface)